Microelectronic Engineer (FPGA/ASIC Design & Verif)

Senior Microelectronic Engineer
* FPGA and Structured ASIC design prototyping ;
* ASIC Frontend Activities and Post-Fab Testing;
* RTL and Functional Verification;
* Digital/Analog Co-simulation;
* Microcontrollers programming;
* Prepare technical specification, test & validation plan;
* PCB Heat sink and thermal consideration;
* Analogic & digital Signal processing;
* Functional Test, Debug, signal's analyzing (Logic Analyser, oscilloscope...);
* Knowledge and implementation of the EMC-relevant standards;
* Knowledge in Circuit diagram, schematic, development and layout of industrial
electronics;
* Knowledge in mixed signal hardware development, Safety, PCB Design, simulation,
review, test & reparation
* Product Specification & certification.

Used methods und tools:
FPGA, Altera Hardcopy, Atmel CAP9H, Modelsim, PlanAhead, ISE, Modelsim, Xilinx ISE,
Planahead & Vivado, Altera Quartus, Hardware acceleration, STM32 uC, PCIe, GigaETH,
VHDL, Verilog, C/C++, TCL/TK , Batch, MS.Net, Eclipse, PIC, signal processing, Power
Electronic, Optoelectronic, Sensors, X-ray image processing, Motor Control et Regulations,
Mentor DxDesigner PCB & Hyperlynx DRC, Spice, Aldec Alint, SIL2, IEC 61131(IEC 62061),
IEC 61508.

10 years

Microelectronic Engineer
* RTL Design (VHDL, Verilog)
* Writing of for Detailed design, implementation report & verification plan documents;
* Verilog RTL, e-verification component (protocol checkers, scoreboard, traffic


generation), PSL assertions coding;
* TCL/Tk & shell scripting;
* Low Power Intended RTL design linting (Coding Rules Checking);
* DFT (Scan Chain test script & Tetramax ATPG);
* Synthesis, STA (Static Timing Analysis);
* DFT (Design For Test) activities;
* Frequency and Voltage domains Crossing;
* Clock Tree Insertion;
* SoC Prototyping on Xilinx & Altera FPGAs;
* Physical verification and prototyping user case on Structured ASIC based SoC.
* BCA/TLM Modelling of On Chip Bus Modules;
* Constrained Random and Formal Verification;
* Assertion Based Verification (SVA, PSL, OVL);
* Modeling and verification using SystemC-SVC & TLM
* Experience in C++ / SystemC Modelling & verification modules coding;
* Verification using eVC (Specman Ellite);
* Experience in Radiation Tolerant Design;
* Embedded linux based C coding (ARM9 cores based SoC);
* Working in an industrial setting and multinational teams;
* Completed product development projects in the area of mixed-signal industrial
electronics, & power electronics field;
* EMC standards and their implementation in design;
* Circuit board technologies, PCB Prototyping & Manufacturing;
* Good hands on experience electrical & electronic Labs equipment;
* Microprocessor and FPGA based boards development;
* Good experience with programming in an embedded environment;
* Familiarity with thermal, safety and reliability consideration for embedded hardware
design;

Used methods und tools:
Synopsys Design Compiler, Cadence Incisive HAL, FPGA, CPLD, ASIC, DSP, VHDL,
Verilog, SystemC-SVC & TLM, Specman Ellite, C/C++, Matlab, TCL/TK, Unix Shell , Perl,
PrimeTime STA, Mentor Graphic Modelsim, SDC, Synopsys TetraMax ATPG, Synopsys
Formality EC, Synopsys PrimeTime STA, Cadence SoC Encounter, ARM9 Cores, Synopsys
Virtualizer Development Kits, System Verilog, UVM, ABV, Incremental Synthesis, Analog-
Digital Co-simulation, ISO 9001-v2008, CMMI Level 5.